Digital design
Static Timing Analysis (STA)
Verilog
System Verilog
UVM
Simulation and Debug
RTL Design
Lint/CDC
Integration learning
FPGA Concepts
Implementing Designs
Validation
HW/SW co-design
Testbench Development
Verification Strategies and planning
Gatelevel Simulation
Coverage
Assertions
SoC Understanding
SoC Integration
Interconnect concepts
SoC Verification
Scripting (Perl & Shell & Python)
Linux
Email etiquette
Communication skills